fast pfet buck controller lm51031 features 1.0 a totem pole output driver high speed oscillator (700 khz max) no stability compensation required lossless short circuit protection vcc monitor 2.0% precision reference programmable soft-start moisture sensitivity level 3 the lm51031 is a switching contoller for use in dc-dc converter s. it can be used in the buck topology with a minimum number of external components. the lm51031 consists of a vcc monitor for controlling the state of the device, 1.0a power driver for cont rolling the gate of a discrete p-channel transistor, fixed frequency os cillator, short circuit protection timer, programmable soft-start, precis ion ordering information reference, fast output voltage monitoring comparator, and outpu t stage driver logic with latch. the high frequency oscillator allows the use of small inductior s and output capacitors, minimizing pc board area and system cost . the programmable soft-start reduces current surges at startup. the short circuit protection timer signifaicantly reduces the duth cycle to approximately 1/30 of its cycle during short circuit conditions . 2008 - ver. 1.0 device marking package LM51031D lm51031 sop-8 htc description ? 1 ? sop-8 pkg typical application (fixed output voltage versions) fi g ure 1. block dia g ram and t yp ical a pp lication
fast pfet buck controller lm51031 maximum ratings (absolute maximum ratings indicate limits beyond which damage to the device may occur ) wave solder (through hole sytle only) (note 1) reflow (smd styles only) (note 2) maximum ratings are those value beyond which device damage con occur. maximum ratings applied to the device are individual stress limit values (not normal operating condit ions) and are not valid simultneously. if these limits are exceeded, device functional operation is no t implied, damage may occur and reliablilty may be affected. 1. 10 sec. maximum. 2. 60 sec. max above 183 package lead description driver supply voltage. 8 v c feedback voltage input. logic supply voltage. soft-start and fault timing capacitor. v gate 20 v 6v a driver supply voltage v c 20 v maximum supply voltage v cc 20 v rating symbol value unit driver output voltage peak output current - 1 c osc , cs, v fb (logic pin) ma operating ambient temperature range t a 0 to 70 operating junction temperature t j 0 to 125 esd (human body model) - 2.0 kv gnd v fb v cc cs 5 6 7 - logic ground. driver pin to gate of external p-ch fet. output power stage ground connection. oscilator frequency programming capacitor. 4 1 2 3 v gate p gnd c osc pin symbol function package pin number 260 peak lead temperature soldering - - 230 peak steady state out current - 200 storage temperature range t s -65 to 150 htc ? 2 ?
fast pfet buck controller lm51031 electrical characteristics (specifications apply for 4.5v v cc 16v, 3v v c 16v, 0 t j 125 , unless otherwise specified.) v fb = 1.0 v; cs = 0.1 uf; v cosc = 2.0 v cs comparator v fb = 1.0 v c gate = 1.0 nf; 1.5 v < v gate < 9.0 v c gate = 1.0 nf; 1.5 v < v gate < 9.0 v 3. guaranteed by design, not 100% tested in production. oscillator frequency charge current khz - - - - ua ua % - 80.0 83.3 680 110 max unit 160 200 240 min typ test conditions characteristic ms ua slow discharge current 2.4 v < v cs < 1.5 v ua 175 264 325 ua 80 fast discharge current 2.55 v > v cs < 2.4 v 4.0 6 10 40.0 66 0.85 1.4 0.2 0.3 0.45 0.7 ms valid fault time 2.6 v > v cs > 2.4 v gate inhibit time ms 2.4 v > v cs > 1.5 v 9.0 15 23 1.250 1.290 1.12 1.225 1.250 1.275 1.210 4.0 v 20 120 mv 1.15 1.19 4ua voltage tracking 70 100 (regulator threshold - fault threshold voltage) - 4.085 - 1.5 4.200 discharge current maximum duty cycle v fb = 1.2v c osc = 470 pf 1.4 v < v cosc < 2.0 v 2.7 v > v cosc > 2.0 v 1 - (t off /t on ) fault duty cycle - 2.5 3.1 4.6 % fault threshold voltage t j = 25 (note 3) v t j = 0 to 125 v 1.15 1.17 1.10 t j = 25 (note 3) v t j = 0 to 125 15 mv threshold line regulation 4.5 v v cc 16 v - mv - input hysteresis voltage input bias current v fb = 0 v -1 power stage v cc = v c = 10 v; v fb = 1.2 v gate dc low saturation voltage v cosc = 1.0v;200 ma sink v gate dc high saturation voltage v 1.2 1.5 2.1 - rise time -25 - 0.866 0.7 1.5 2.4 2.6 fall time -25 v fb = 1.5 v v cs = when gate goes high - - 0.4 0.725 4.500 v v cc monitor turn-on threshold - 4.100 4.300 0 v < v cs < 2.5 v - 60 ns 60 ns -6 200 mv turn-off threshold short circuit timer c fb comparator v cosc = v cs = 2.0 v regulator threshold voltage charge current 1.0 v < v cs < 2.0 v start fault inhibit time hysteresis - 65 130 v cs = 1.5 v - ma current drain 4.5 v < v cc < 16 v, gate switching 4.5 shutdown i cc v cc = 4.0 i c 3.0 v < v c < 16 v, gate nonswitching i cc fault enable cs voltage max cs voltage fault detect voltage fault inhibit voltage hold off release voltage regulator threshold voltage clamp minimum v cs v fb = 0 v 4.0 ma 6.0 2.7 900 a htc 4.415 v - 1.0 1.035 2.5 - - - v v v v ? 3 ? v cosc = 2.7v;200 ma source; v c =v gate v v 500
fast pfet buck controller lm51031 theory of operation control scheme the lm51031 monitors and the output voltage to operate. this me thod of control does not its require any determine when to turn on the pfet. if v fb falls loop stability compensation. below the internal reference voltage of 1.25v during startup theoscillators charge cycle, the pfet is turned on the lm51031 has an externally programmable soft start and remains on for the duration.of the charge time. feature th at allows the output voltage to come up the pfet gets turned off and remains off during slowly prevent ing voltage overshoot on the output. the oscillators discharge time with the maximum at startup, th e voltage on all pins is zero. as v cc rises, duty cycle to 80%. it requires 7mv typical, and the v c voltage along with the internal resistor r g keeps 20mv maximum ripple on the v fb pin is required to htc ? 4 ? figure 2. block diagram
fast pfet buck controller lm51031 the pfet off. as v cc and v c continue to rise, the lossless short circuit protection oscillator capacitor (c osc ) and soft start/fault the lm51031 has lossless short circuit protection timing capacitor(cs) charges via internal current since there i s no current sense resistor reguired. sources. c osc gets charged by the current source when the voltage at the cs p in (the fault timing ic and cs gets charged by the it source capacitor voltage) rea ches 2.5v during startup, the combination described by: fault timing circuitry is enabled. dur ing normal operation the cs voltage is 2.6v. during a short circuit or a transient condition, the output voltage moves lower and the voltage at v fb drops. if v fb drops below 1.15v, the output of the fault comparator goes high and the the internal holdoff comparator ensures that the lm51031 goes in to a fast discharge mode. the fault external pfet is off until v cs > 0.7v, preventing the timing capacitor, cs, discharges to 2.4v . if the v fb gate flip-flop (f2) from being set. this allows the voltage is s till below 1.15v when the cs pin reaches oscillator to reach its operating frequency before 2.4v, a valid fault condition has been detected. the enabling the drive output. soft start is obtained by slow discha rge comparator output goes high and clamping the v fb comparators (a6) reference input enables gate g5 which sets th e slow discharge flip to approximately 1/2 of the voltage at the cs pin flop. the vga te flip flop resets and the output switch is during startup, permitting the control loop and the turned off. the fault timing capacitor is slowly output voltage to slowly increase. once the cs pin discharged to 1.5v. the lm51031 then enters a normal charges above the holdoff comparator trip point of startup routi ne. if the fault is still present when the 0.7v, the low feedback to the v fb comparator sets fault timing capacitor voltage reaches 2.5v, th e fast and the gate flip-flop during cosc s charge cycle. slow discharge cycles repeat as shown in figure 2. once the gate flip-flop is set, v gate goes low and if the v fb voltage is above 1.15v when cs reaches turns on the pfet. when v cs exceeds 2.4v, the cs 2.4v a fault condition is not detected, no rmal operation charge sense comparator (a4) sets the v fb resumes and cs charges back to 2.6v. this reduces the comparator reference to 1.25v completing the startup chance of e rroneously detecting a load transient as a cycle. fault condition. htc ? 5 ? figure 3. voltage on start capacitor (v gs ), the gate (v gate ), and in the feedback loop (v fb ), during startup, normal and fault conditions
fast pfet buck controller lm51031 buck regulator operation a block diagram of a typical buck regulator is shown resistors r1 and r2 and he reference voltage v ref , in figure 4. if we assume that the output transistor is the pow er transistor q1 switches on and current flows initially off, and the system is in discontinuous through the in ductor to the output. the inductor current operation, the inductor current il is zero and the rises at a r ate determined by (v in ? v out )/l. output voltage is at its nominal value. the current the duty cy cle (or on time) for the lm51031 is limited drawn by the load is supplied by the output to 80%. if output v oltage remains to 80%. if output volta g capacitor c o . when the voltage across c o drops remains higher than nominal during the entire c osc below the threshold established by the feedback change time, th e q1 does not turn on, skipping the pulse applications information lm51031 design example specications 12 v to 5.0 v, 3.0 a buck controller continuous conduction mode is given by: vin = 12 v 20% (i.e. 14.4 v max, 121 v nom, 9.6 v min) vout = 5.0 v2% iout = 0.3 a to 3.0 a where: output ripple voltage < 50 mv max v sat = r ds (on) i out max and r ds ( on ) is the value a t efficiency > 80% tj 100c. f sw = 200 khz if vf = 0.60 v and vsat = 0.60 v then the above equa ti becomes: 1) duty cycle estimates since the maximum duty cycle d, of the lm51031 is limited to 80% min, it is necessary to estimate the duty cycle for the various input condidtions over the complete operating range. the duty cycle for a buck regulator operating in a htc ? 6 ? figure 4. buck regulator block diagram
fast pfet buck controller lm51031 2) switching frequency and on and off time calculations impedance aluminum are less expensive. given that f sw = 200 khz and d max = 0.80 of suppliers and are the best choice for surface mount solid tantalum chip capacitors are available from a numb of suppliers and are the best choice for surface mount applications. the output capacitor limits the output ripple voltage. th e lm51031 needs a maximum of 20 mv of output ripple fo r the feedback comparator to change state. if we assume that all the inductor ripple current flows through the outpu t capacitor and that it is an ideal capacitor (i.e. zero esr), 3) oscillator capacitor selection the minimum capacitance needed to limit the output rippl e the switching frequency is set by cosc, whose to 50 mv peak?t o?peak is given by: value is given by: the minimum esr needed to limit the output voltage ripple to 50 mv peak?to?peak is: 4) inductor selection the output capacitor should be chosen so that its esr is the inductor value is chosen for continuous mode less than 83 m. operation down to 0.3 amps. during the minimum off time, the rip ple current is 0.4 a the ripple current ?i = 2 i outmin = 2 0.3 a and the output voltage ripple will be: = 0.6 a this is the minimum value of inductor to keep the 6) vfb divider ripple current < 0.6 a during normal operation. a smaller inductor will result in larger ripple current. ripple current at a minimum off time is: the input bi as current to the comparator is 4.0 ua. the resistor divider current should be considerably higher than this to ensure that there is sufficient bias current. if we the core must not saturate with the maximum choose the divide r current to be at least 250 times the bi a expected current, here given by: current this permits a divider current of 1.0 ma and simplifies the calculations. 5) output capacitor let r2 = 1.0 k the output capacitor and the inductor form a low rearranging the divider equation gives: pass filter. the output capacitor should have a low esl and esr. low impedance aluminum electrolytic, tantalum or organic semiconductor capacitors are a good choice for an output capacitor. low htc ? 7 ?
fast pfet buck controller lm51031 7) divider bypass capacitor crr since the feedback resistors divide the output voltage by a factor of 4.0, i.e. 5.0 v/1.25 v = 4.0, the fast discharge time occurs when a fault is first it follows that the output ripple is also divided by detected. the cs capacitor is discharged from 2.5 v to 2 four. this would require that the output ripple be at comparator. we use a capacitor crr to act as an least 60 mv (4.0 15 mv) to trip the feedback ac short. the ripple voltage frequency is equal to the where ifa stdischarge is 66 ua typical. switching frequency so we choose crr = 1.0 nf. 8) soft?start and fault timing capacitor cs the recharge time is the time for cs to charge from 1.5 cs performs several important functions. first it to 2.5 v. provides a delay time for load transients so that the ic does not enter a fault mode every time the load changes abruptly. secondly it disables the fault circuitry during startup, it also provides soft?start where i charge is 264 ua typical. by clamping the reference voltage during startup, allowing it to rise slowly, and, finally it controls the hiccup short circuit protection circuitry. this reduces the fa ult time is given by: the duty cycle to approximately 0.035 during short circuit conditions. an important consideration in calculating cs is that its voltage does not reach 2.5 v (the voltage at which the fault detect circuitry for th is circuit is enabled) before vfb reaches 1.15 v otherwise the power supply will never start. if the vfb pin reaches 1.15 v, the fault timing comparator will a larger value of cs will increase the fault time out time discharge cs and the supply will not start. for the but will al so increase the soft?start time. vfb voltage to reach 1.15 v the output voltage must be at least 4 1.15 = 4.6 v. if we choose an 9) input capacitor arbitrary startup time of 900 s, the value of cs is: the inpu t capacitor reduces the peak currents drawn from the input supply and reduces the noise and ripple voltage on the vcc and vc pins. this capacitor must als o ensure that the vcc remains above the uvlo voltage in the event of an output short circuit. a low esr capacitor the fault time is the sum of the slow discharge time output s hort circuit. a low esr capacitor of at least 100 u the fast discharge time and the recharge time. it is is good. a ceramic surface mount capacitor should also dominated by the slow discharge time. be connected between vcc a nd ground to filter high the first parameter is the slow discharge time, it is frequency noise. the time for the cs capacitor to discharge from 2.4 v to 1.5 v and is given by: 10) mosfet selection the lm51031 drives a p?channel mosfet. the vgate pin swings from gnd to vc. the type of p?ch fet used depends on the operating conditions but for input voltage where idischarge is 6.0 ua typical. below 7.0 v a logic level fet should be used. ? 8 ? htc
fast pfet buck controller lm51031 a p?ch fet with a continuous drain current (id) rating greater than the maximum output current is required. the gate?to?source voltage vgs and source breakdown voltage should be chosen based on the input supply voltage. the power dissipation due to the conduction losses is given by: where the power dissipation of the p?ch fet due to the switching losses is given by: where tr = rise time. 11) diode selection the flyback or catch diode should be a schottky diode because of its fast switching ability and low forward voltage drop. the current rating must be at least equal to the maximum output current. the breakdown voltage should be at least 20 v for this 12 v application. the diode power dissipation is given by: htc ? 9 ?
|
